Overcoming I/O bottleneck in superconducting quantum computing: multiplexed qubit control with ultra-low-power, base-temperature cryo-CMOS multiplexer

Large-scale superconducting quantum computing systems entail high-fidelity control and readout of large numbers of qubits at millikelvin temperatures, resulting in a massive input-output bottleneck. Cryo-electronics, based on complementary metal-oxide-semiconductor (CMOS) technology, may offer a scalable and versatile solution to overcome this bottleneck. However, detrimental effects due to cross-coupling between the electronic and thermal noise generated during cryo-electronics operation and the qubits need to be avoided. Here we present an ultra-low power radio-frequency (RF) multiplexing cryo-electronics solution operating below 15 mK that allows for control and interfacing of superconducting qubits with minimal cross-coupling. We benchmark its performance by interfacing it with a superconducting qubit and observe that the qubit's relaxation times ($T_1$) are unaffected, while the coherence times ($T_2$) are only minimally affected in both static and dynamic operation. Using the multiplexer, single qubit gate fidelities above 99.9%, i.e., well above the threshold for surface-code based quantum error-correction, can be achieved with appropriate thermal filtering. In addition, we demonstrate the capability of time-division-multiplexed qubit control by dynamically windowing calibrated qubit control pulses. Our results show that cryo-CMOS multiplexers could be used to significantly reduce the wiring resources for large-scale qubit device characterization, large-scale quantum processor control and quantum error correction protocols.Comment: 16+6 pages, 4+1+5 figures, 1 tabl

A 1.8 Ghz Low-Phase-Noise CMOS VCO using optimized Hollow Spiral Inductors

status: publishe

6.3 4G Terminals: How are We Going to Design Them?

Fourth-generation wireless communication systems (4G) will have totally different requirements than what front-end designers have been coping with up to now. Designs must be targeted to multi-mode and reconfigurability, leading to the concept of a “software-defined radio”. A large part of such a radio will be integrated into a complex SoC, where the substrate noise coupling problem must be solved. However, for an optimal implementation of the complete system, including e.g. PA, RF filters and antenna, different technologies must be combined in a single package, merging the worlds of microwave ‘s-parameter ’ designers and IC ‘spice ’ designers. Design and simulation environments efficiently combining the assets of both are needed. At the same time, optimized mixed-signal radio architectures including digital compensation techniques that overcome the limitations and inaccuracies of the analog front-end must be developed. Again, efficiently designing and simulating such mixed analog/digital architectures requires an optimized tool capable of combining RF simulation techniques with digital system model simulation

A design approach for power-optimized fully reconfigurable Delta Sigma A/D converter for 4G radios

This paper presents a novel design approach for fully reconfigurable low-voltage delta-sigma analog-digital converters for next-generation wireless applications. This approach guides us to find the power-optimal solution corresponding to the specifications of various wireless standards by exploring single-loop feedback and feedforward topologies with different filter order, number of quantizer bits, and oversampling ratios. Unlike previous multimode designs, this approach provides a better power efficiency. Based on this approach, a system-level design of a digitally programmable delta-sigma modulator for 4G radios is presented.status: publishe

A systematic design methodology for power-optimal design of high-order multi-bit continuous-time Delta-Sigma modulators

In this paper a systematic design methodology for high-order multi-bit continuous-time Delta-Sigma modulators is proposed. It provides a straightforward method for determining the coefficients of the modulator. The method is illustrated for a 4th-order 4-bit modulator with OSR of 8, while 20 MHz signal bandwidth and 12 bit resolution is achieved. The required GBW of the first integrator is less than 1.5 times the sampling frequency, which greatly reduces the overall power consumption.status: publishe